View CAT24C32ZD2E-GT2_3767409.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 ? catalyst semiconductor, inc. characteristics subject to change without notice doc. no. md-1101, rev. j cat24c32 32-kb i 2 c cmos serial eeprom pin configuration functional symbol features supports standard and fast i 2 c protocol 1.7 v to 5.5 v supply voltage range 32-byte page write buffer hardware write protection for entire memory schmitt triggers and noise suppression filters on i 2 c bus inputs (scl and sda). low power cmos technology 1,000,000 program/erase cycles 100 year data retention industrial and extended temperature range rohs-compliant pdip, soic, tssop, tdfn and udfn 8-lead packages pdip (l) soic (w) tssop (y) tdfn (vp2) udfn (hu3) v cc v ss sd a scl wp cat24c32 a 2 , a 1 , a 0 device description the cat24c32 is a 32-kb cmos serial eeprom devices, internally organized as 128 pages of 32 bytes each. it features a 32-byte page write buffer and supports both the standard (100 khz) as well as fast (400 khz) i 2 c protocol. external address pins make it possible to address up to eight cat24c32 devices on the same bus. 8 7 6 5 v cc wp scl sda a 2 a 0 a 1 v ss 1 2 3 4 for the location of pin 1, please consult the corresponding package drawing. pin functions a 0 , a 1 , a 2 device address sda serial data scl serial clock wp write protect v cc power supply v ss ground * the green & gold seal identi? es rohs-compliant packaging, using nipdau pre-plated lead frames. for ordering information details, see page 16.
cat24c32 2 doc. no. md-1101, rev. j ? catalyst semiconductor, inc. characteristics subject to change without notice absolute maximum ratings (1) storage temperature -65c to +150c voltage on any pin with respect to ground (2) -0.5 v to +6.5 v reliability characteristics (3) symbol parameter min units n end (4) endurance 1,000,000 program/ erase cycles t dr data retention 100 years d.c. operating characteristics v cc = 1.8 v to 5.5 v, t a = -40c to +125c and v cc = 1.7 v to 5.5 v, t a = -20c to +85c, unless otherwise speci?ed. symbol parameter test conditions min max units i ccr read current read, f scl = 400khz 1 ma i ccw write current write, f scl = 400khz 2 ma i sb standby current all i/o pins at gnd or v cc t a = -40c to +85c 1 a t a = -40c to +125c 2 i l i/o pin leakage pin at gnd or v cc t a = -40c to +85c 1 a t a = -40c to +125c 2 v il input low voltage -0.5 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol1 output low voltage v cc < 2.5 v, i ol = 3.0ma 0.4 v v ol2 output low voltage v cc < 2.5 v, i ol = 1.0ma 0.2 v pin impedance characteristics v cc = 1.8 v to 5.5 v, t a = -40c to +125c and v cc = 1.7 v to 5.5 v, t a = -20c to +85c, unless otherwise speci?ed. symbol parameter conditions max units c in (3) sda i/o pin capacitance v in = 0 v, t a = 25c, f = 1.0mhz 8 pf c in (3) input capacitance (other pins) v in = 0 v, t a = 25c, f = 1.0mhz 6 pf i wp (5) wp input current v in < v ih 200 a v in > v ih 1 note: (1) stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this speci?cation is not implied. exposure to any absolute maximum rating for extended periods may af fect device performance and reliability. (2) the dc input voltage on any pin should not be lower than -0.5 v or higher than v cc + 0.5 v. during transitions, the voltage on any pin may undershoot to no less than -1.5 v or overshoot to no more than v cc + 1.5 v, for periods of less than 20 ns. (3) these parameters are tested initially and after a design or process change that affects the parameter according to appropriate aec-q100 and jedec test methods. (4) page mode, v cc = 5 v, 25c (5) when not driven, the wp pin is pulled down to gnd internally. for improved noise immunity, the internal pull-down is relatively strong; therefore the external driver must be able to supply the pull-down current when attempting to drive the input high. to conserve power, as the input level exceeds the trip point of the cmos input buffer (~ 0.5 x v cc ), the strong pull-down reverts to a weak current source.
cat24c32 3 doc. no. md-1101, rev. j ? catalyst semiconductor, inc. characteristics subject to change without notice a.c. characteristics (1) v cc = 1.8 v to 5.5 v, t a = -40c to +125c and v cc = 1.7 v to 5.5 v, t a = -20c to +85c, unless otherwise speci?ed. symbol parameter standard fast units min max min max f scl clock frequency 100 400 khz t hd:sta start condition hold time 4 0.6 s t low low period of scl clock 4.7 1.3 s t high high period of scl clock 4 0.6 s t su:sta start condition setup time 4.7 0.6 s t hd:dat data in hold time 0 0 s t su:dat data in setup time 250 100 ns t r sda and scl rise time 1000 300 ns t f (2) sda and scl fall time 300 300 ns t su:sto stop condition setup time 4 0.6 s t buf bus free time between stop and start 4.7 1.3 s t aa scl low to data out valid 3.5 0.9 s t dh data out hold time 100 100 ns t i (2) noise pulse filtered at scl and sda inputs 100 100 ns t su:wp wp setup time 0 0 s t hd:wp wp hold time 2.5 2.5 s t wr write cycle time 5 5 ms t pu (2, 3) power-up to ready mode 1 1 ms note: (1) test conditions according to a.c. test conditions table. (2) tested initially and after a design or process change that affects this parameter. (3) t pu is the delay between the time v cc is stable and the device is ready to accept commands. a.c. test conditions input levels 0.2 x v cc to 0.8 x v cc input rise and fall times 50 ns input reference levels 0.3 x v cc , 0.7 x v cc output reference levels 0.5 x v cc output load current source: i ol = 3 ma (v cc 2.5 v); i ol = 1 ma (v cc < 2.5 v); c l = 100 pf
cat24c32 4 doc. no. md-1101, rev. j ? catalyst semiconductor, inc. characteristics subject to change without notice power-on reset (por) each cat24c32 incorporates power-on reset (por) circuitry which protects the internal logic against powering up in the wrong state. the device will power up into standby mode after v cc exceeds the por trigger level and will power down into reset mode when v cc drops below the por trigger level. this bi-directional por behavior protects the device against brown-out failure following a temporary loss of power. pin description scl: the serial clock input pin accepts the clock signal generated by the master. sda: the serial data i/o pin accepts input data and delivers output data. in transmit mode, this pin is open drain. data is acquired on the positive edge, and is delivered on the negative edge of scl. a 0 , a 1 and a 2 : the address inputs set the device ad - dress that must be matched by the corresponding slave address bits. the address inputs are hard-wired high or low allowing for up to eight devices to be used (cascaded) on the same bus. when left ?oating, these pins are pulled low internally. wp: when pulled high, the write protect input pin inhibits all write operations. when left ?oating, this pin is pulled low internally. functional description the cat24c32 supports the inter-integrated circuit (i 2 c) bus protocol. the protocol relies on the use of a master device, which provides the clock and directs bus traf?c, and slave devices which execute requests. the cat24c32 operates as a slave device. both master and slave can transmit or receive, but only the master can assign those roles. i 2 c bus protocol the 2-wire i 2 c bus consists of two lines, scl and sda, connected to the v cc supply via pull-up resistors. the master provides the clock to the scl line, and either the master or the slaves drive the sda line. a 0 is transmitted by pulling a line low and a 1 by letting it stay high. data transfer may be initiated only when the bus is not busy (see a.c. characteristics). during data transfer, sda must remain stable while scl is high. start/stop condition an sda transition while scl is high creates a start or stop condition (figure 1). the start consists of a high to low sda transition, while scl is high. absent the start, a slave will not respond to the master. the stop completes all commands, and consists of a low to high sda transition, while scl is high. device addressing the master addresses a slave by creating a start condition and then broadcasting an 8-bit slave address. for the cat24c32, the ?rst four bits of the slave address are set to 1010 (ah); the next three bits, a 2 , a 1 and a 0 , must match the logic state of the similarly named input pins. the r/ w bit tells the slave whether the master intends to read (1) or write (0) data (figure 2). acknowledge during the 9 th clock cycle following every byte sent to the bus, the transmitter releases the sda line, allow - ing the receiver to respond. the receiver then either acknowledges (ack) by pulling sda low, or does not acknowledge (noack) by letting sda stay high (figure 3). bus timing is illustrated in figure 4.
cat24c32 5 doc. no. md-1101, rev. j ? catalyst semiconductor, inc. characteristics subject to change without notice figure 3. acknowledge timing figure 2. slave address bits 1 8 9 start scl from master bus release delay (transmitter) bus release delay (receiver) data output from transmitter data output from receiver ack delay ( t aa ) ack setup ( t su:dat ) start condition stop condition sda scl figure 1. start/stop timing figure 4. bus timing t high scl sda in sda out t low t f t low t r t buf t su:s to t su:d at t hd:d at t hd:s ta t su:s ta t aa t dh 1 0 1 0 device address a 2 a 1 a 0 r/w
cat24c32 6 doc. no. md-1101, rev. j ? catalyst semiconductor, inc. characteristics subject to change without notice write operations byte write to write data to memory, the master creates a start condition on the bus and then broadcasts a slave ad - dress with the r/ w bit set to 0. the master then sends two address bytes and a data byte and concludes the session by creating a stop condition on the bus. the slave responds with ack after every byte sent by the master (figure 5). the stop starts the internal write cycle, and while this operation is in progress (t wr ), the sda output is tri-stated and the slave does not acknowl - edge the master (figure 6). page write the byte write operation can be expanded to page write, by sending more than one data byte to the slave before issuing the stop condition (figure 7). up to 32 distinct data bytes can be loaded into the internal page write buffer starting at the address provided by the master. the page address is latched, and as long as the master keeps sending data, the internal byte address is incremented up to the end of page, where it then wraps around (within the page). new data can therefore replace data loaded earlier. following the stop, data loaded during the page write session will be written to memory in a single internal write cycle (t wr ). acknowledge polling as soon (and as long) as internal write is in progress, the slave will not acknowledge the master. this feature enables the master to immediately follow-up with a new read or write request, rather than wait for the maximum speci?ed write time (t wr ) to elapse. upon receiving a noack response from the slave, the master simply re - peats the request until the slave responds with ack. hardware write protection with the wp pin held high, the entire memory is protected against write operations. if the wp pin is left ?oating or is grounded, it has no impact on the write operation. the state of the wp pin is strobed on the last falling edge of scl immediately preceding the 1 st data byte (figure 8). if the wp pin is high during the strobe interval, the slave will not acknowledge the data byte and the write request will be rejected. delivery state the cat24c32 is shipped erased, i.e., all bytes are ffh.
cat24c32 7 doc. no. md-1101, rev. j ? catalyst semiconductor, inc. characteristics subject to change without notice figure 7. page write sequence figure 6. write cycle timing sla ve address s a c k a c k a c k s t a r t a c k s t o p a c k a c k p a c k bus activity: master slave n = 1 p 31 address byte address byte data byte n data byte n+1 data byte n+p t wr st op condition st ar t condition address ac k 8 th bi t byte n scl sd a figure 5. byte write sequence sla ve address s a * * * * c k a c k a c k s t o p p s t a r t a c k * a 15 a 12 are don't care bits. bus activity: master slave address byte data byte a 15 a 8 a 7 a 0 data byte d 7 d 0 figure 8. wp timing 1 8 9 1 8 a 7 a 0 d 7 d 0 t su:w p t hd:w p address byte data byte scl sda wp
cat24c32 8 doc. no. md-1101, rev. j ? catalyst semiconductor, inc. characteristics subject to change without notice read operations immediate read to read data from memory, the master creates a start condition on the bus and then broadcasts a slave ad - dress with the r/ w bit set to 1. the slave responds with ack and starts shifting out data residing at the current address. after receiving the data, the master responds with noack and terminates the session by creating a stop condition on the bus (figure 9). the slave then returns to standby mode. selective read to read data residing at a speci?c address, the selected address must ?rst be loaded into the internal address register. this is done by starting a byte write sequence, whereby the master creates a start condition, then broadcasts a slave address with the r/w bit set to 0 and then sends two address bytes to the slave. rather than completing the byte write sequence by sending data, the master then creates a start condition and broadcasts a slave address with the r/ w bit set to 1. the slave responds with ack after every byte sent by the master and then sends out data residing at the selected address. after receiving the data, the master responds with noack and then terminates the session by creating a stop condition on the bus (figure 10). sequential read if, after receiving data sent by the slave, the master responds with ack, then the slave will continue transmit - ting until the master responds with noack followed by stop (figure 11). during sequential read the internal byte address is automatically incremented up to the end of memory, where it then wraps around to the beginning of memory.
cat24c32 9 doc. no. md-1101, rev. j ? catalyst semiconductor, inc. characteristics subject to change without notice figure 11. sequential read sequence s t o p p sla ve address a c k a c k a c k n o a c k a c k data byte n data byte n+1 data byte n+2 data byte n+x bus activity: master slave figure 10. selective read sequence sla ve address s a c k a c k a c k s t a r t sla ve s a c k s t a r t p s t o p address byte address byte address n o a c k data byte bus activity: master slave figure 9. immediate read sequence and timing scl sd a 8 th bit st op no ac k da ta out 8 9 sla ve address s a c k data byte n o a c k s t o p p s t a r t bus activity: master slave
cat24c32 10 doc. no. md-1101, rev. j ? catalyst semiconductor, inc. characteristics subject to change without notice pdip 8-lead 300mil (l) notes: (1) all dimensions are in millimeters. (2) complies with jedec standard ms-001 . for current tape and reel information, download the pdf ?le from: http://www.catsemi.com/documents/tapeandreel.pdf. e1 d a l e b b2 a1 a2 e eb c to p view side view end view pin # 1 identifica tion pa ckage outline dra wing pdip 8-lead 300mils (p , l) doc. no. pdip8-001-01 01/21/08 notes: (1) all dimensions are in millimeters. (2) complies with jedec ms-001. symbol min nom max a 5.33 a1 0.38 a2 2.92 3.30 4.95 b 0.36 0.46 0.56 b2 1.14 1.52 1.78 c 0.20 0.25 0.36 d 9.02 9.27 10.16 e 7.62 7.87 8.25 e 2.54 bsc e1 6.10 6.35 7. 11 eb 7.87 10.92 l 2.92 3.30 3.80 package outline drawings
cat24c32 11 doc. no. md-1101, rev. j ? catalyst semiconductor, inc. characteristics subject to change without notice e1 e a a1 h l c e b d pin # 1 identifica tion to p view side view end view pa ckage informa tion soic 8-lead 150 mils (s, j; v, w) doc. no. soic8-002-01 07/24/2007 notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec ms-012. a 1 .35 1 .7 5 a1 0.10 0.25 b 0.33 0 .5 1 c 0.19 0 .2 5 d 4.80 5 .0 0 e 5.80 6 .2 0 e1 3.80 4.00 e 1.27 bsc h 0.25 0 .5 0 l 0.40 1 .2 7 0o 8 o symbol min nom max notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec standard ms-012. for current tape and reel information, download the pdf ?le from: http://www.catsemi.com/documents/tapeandreel.pdf. soic 8-lead 150mil (w)
cat24c32 12 doc. no. md-1101, rev. j ? catalyst semiconductor, inc. characteristics subject to change without notice notes: (1) all dimensions are in millimeters. (2) complies with jedec standard mo-153. for current tape and reel information, download the pdf ?le from: http://www.catsemi.com/documents/tapeandreel.pdf. a2 e1 e a1 e b d c a to p view side view end view 1 l1 l doc. no. tssop8-004-01 06/21/07 symbol min nom max a 1 .2 0 a 1 0.05 0.15 a 2 0.80 0.90 1.05 b 0.19 0 .3 0 c 0.09 0 .2 0 d 2.90 3.00 3.10 e 6.30 6.40 6.50 e 1 4.30 4.40 4.50 e 0.65 bsc l 1.00 re f l 1 0.50 0.60 0.75 1 0 8 tssop 8-lead (y)
cat24c32 13 doc. no. md-1101, rev. j ? catalyst semiconductor, inc. characteristics subject to change without notice e d pin #1 identifica tion pin #1 identifica tion dap size 2.6 x 3.3mm det ail a d2 a2 a3 a1 a b l e e2 a a1 to p view side view bott om view front view det ail a doc. no. tdfn-s-msop8-035-01 08/24/07 pa ckage informa tion tdfn-s-msop 8-pad 3 x 4.9mm (rd2, zd2) notes: (1) all dimensions are in millimeters. (2) complies with jedec mo-229. symbol min nom max a 0.70 0.75 0.8 0 a1 0.00 0.02 0.05 a2 0.45 0.55 0.65 a3 0.20 ref b 0.25 0.30 0.35 d 2.90 3.00 3.10 d2 0.90 1.00 1.10 e 4.80 4.90 5.00 e2 0.90 1.00 1.10 e 0.65 ty p l 0.50 0.60 0.70 notes: (1) all dimensions are in millimeters. angles in degree. (2) complies with jedec standard mo-229. for current tape and reel information, download the pdf ?le from: http://www.catsemi.com/documents/tapeandreel.pdf. tdfn 8-lead 3 x 4.9mm (zd2)
cat24c32 14 doc. no. md-1101, rev. j ? catalyst semiconductor, inc. characteristics subject to change without notice notes: (1) all dimensions are in millimeters, angles in degrees. (2) complies with jedec standard mo-229. for current tape and reel information, download the pdf ?le from: http://www.catsemi.com/documents/tapeandreel.pdf. pin# 1 identific atio n e2 e a3 e b d a2 to p view side view bott om view pin#1 index area front view a1 a l d2 pa ckage outline dra win g tdfn 8-pad 2 x 3mm (sp2, vp2) doc. no. tdfn8-008-01 08/24/07 notes: (1) all dimensions are in millimeters. (2) complies with jedec mo-229. symbol m in nom ma x a 0.70 0.75 0.80 a1 0.00 0.02 0.05 a2 0.45 0.55 0.65 a3 0.20 ref b 0.20 0.25 0.30 d 1.90 2.00 2.10 d2 1.30 1.40 1.50 e 2.90 3.00 3.10 e2 1.20 1.30 1.40 e 050 ty p l 0.20 0.30 0.40 tdfn 8-pad 2 x 3mm (vp2)
cat24c32 15 doc. no. md-1101, rev. j ? catalyst semiconductor, inc. characteristics subject to change without notice notes: (1) all dimensions are in millimeters, angles in degrees. (2) complies with jedec standard mo-229. for current tape and reel information, download the pdf ?le from: http://www.catsemi.com/documents/tapeandreel.pdf. e2 d2 k l e pin #1 index area pin #1 identifica tion dap size 1.3 x 1.8 det ail a d a1 b e a to p view side view front view det ail a bott om view a3 a a1 pa ckage outline dra win g udfn 8-pad 2 x 3mm (hu3) doc. no. udfn8-032-02 08/29/07 notes: (1) all dimensions are in millimeters. (2) complies with jedec mo-229. symbol min nom max a 0.45 0.50 0.55 a1 0.00 0.02 0.05 a3 0.127 ref b 0.20 0.25 0.30 d 1.90 2.00 2.10 d2 1.50 1.60 1.70 e 2.90 3.00 3.10 e2 0.10 0.20 0.30 e 0.50 ty p k 0.10 ref l 0.30 0.35 0.40 udfn 8-pad 2 x 3mm (hu3)
cat24c32 16 doc. no. md-1101, rev. j ? catalyst semiconductor, inc. characteristics subject to change without notice for product top mark codes, click here: http://www.catsemi.com/techsupport/producttopmark.as p example of ordering information prefix device # suffix 24c32 y i product number 24c32 cat temperature range i = industrial (-40 c to +85 c) e = extended (-40 c to +125 c) company id package l: pdip w: soic, jedec y: tssop zd2: tdfn (3x4.9) (5) vp2: tdfn (2x3) hu3: udfn (2x3) t3 g C t: tape & reel 2: 2000/reel (5) 3: 3000/reel lead finish g: nipdau notes: (1) all packages are rohs-compliant (lead-free, halogen-free). (2) the standard lead ?nish is nipdau. (3) the device used in the above example is a cat24c32yi-gt3 (tssop, industrial temperature, nipdau, tape & reel, 3,000/reel). (4) for additional package and temperature options, please contact your nearest catalyst semiconductor sales of? ce. (5) tdfn, zd2 is only available in 2000 pcs/reel, i.e., cat24c32zd2i-t2. the tdfn 3x4.9mm (zd2) is not recommended for new designs.
cat24c32 17 doc. no. md-1101, rev. j ? catalyst semiconductor, inc. characteristics subject to change without notice revision history date revision comments 10/07/05 a initial issue 11/15/05 b update ordering information add tape and reel speci?cations 02/02/06 c update ordering information 08/23/06 d updated device description, supporting text and ?gures, package outlines, package marking and ordering information. updated and re-formatted d.c. characteristics presentation. updated and re-formatted a.c. characteristics presentation to re?ect standard (100 khz) and fast (400 khz) operation over the full voltage range. 09/08/06 e remove package markings 02/12/07 f update tdfn 8 lead (3x4.9mm) package 03/20/07 g add tdfn 8-lead (2x3mm) package 04/17/07 h add to pin con?guration and example of ordering information not recommended for new design. note for the zd2 package. update pin impedance characteristics 06/27/07 i add extended temperature range update d.c. operating characteristics table update all package outline drawing add md- to document number 03/20/08 j add udfn 8-lead package to pin con?guration update features update d.c. operating characteristics update pin impedance characteristics update a.c. characteristics update package outline drawings add udfn 8-lead package outline drawing update example of ordering information
catalyst semiconductor, inc. corporate headquarters 2975 stender way santa clara, ca 95054 phone: 408.542.1000 fax: 408.542.1200 www.catsemi.com publication #: md-1101 revison: j issue date: 03/20/08 copyrights, trademarks and patents trademarks and registered trademarks of catalyst semiconductor include each of the following: adaptive analog?, beyond memory?, dpp?, ezdim?, ldd?, minipot?, quad-mode? and quantum charge programmable? catalyst semiconductor has been issued u.s. and foreign patents and has patent applications pending that protect its products. catalyst semiconductor makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability arising out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semiconductor product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. products with data sheets labeled advance information or preliminary and other products described herein may not be in production or offered for sale. catalyst semiconductor advises customers to obtain the current version of the relevant product information before placing orders. cir cuit diagrams illustrate typical semiconductor applications and may not be complete.

▲Up To Search▲

Price & Availability of CAT24C32ZD2E-GT2

	To Download CAT24C32ZD2E-GT2 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .